A Meta-Interpreter for Circuit-Extraction

TitleA Meta-Interpreter for Circuit-Extraction
Publication TypeConference Paper
Year of Publication1994
AuthorsKrishnaprasad Thirunarayan
Conference NameA Meta-Interpreter for Circuit-Extraction
Abstract

The design of a VLSI circuit consists of a description of the circuit in terms of its components and subcomponents, at various levels of detail. To verify that the layout of a VLSI circuit conforms to its design, one needs to work backwards from the lowest-level description of the circuit and recognize the higher-level components it constitutes. This paper is concerned with the application of logic programming techniques in the formal verification of the structural correctness of the VLSI circuit layouts. In particular, we review Michael Dukes' Generalized Extraction System (GES) that compiles design descriptions into a set of extraction rules, and then study the benefits and the limitations of using a meta-interpreter approach to extraction.

Full Text

Krishnaprasad Thirunarayan, 'A Meta-Interpreter for Circuit-Extraction', In: Proceedings of the IEEE 1994 National Aerospace and Electronics Conference (NAECON 1994) , Dayton, OH, pp. 680-684, May 1994.
pages: 680-684
year: 1994
venue name: IEEE 1994 National Aerospace and Electronics Conference (NAECON 1994)
hasURL: http://knoesis.wright.edu/library/publications/MetaInterp1994.pdf
hasBookTitle: Proceedings of the IEEE 1994 National Aerospace and Electronics Conference (NAECON 1994)